Design and VLSI implementation of an access processor for a decoupled architecture

Decoupled computer architectures provide high scalar performance by exploiting the ne{grained parallelism existing between the access and execute functions in a computer program. These architectures employ an access processor to perform data fetch ahead of demand by the execute process. Some of the decoupled archi-tectures employ identical access and execute processors, but special processors to eeciently access data structures have also been proposed. In this paper, we present the design of an access processor targeted for VLSI implementation. The hardware elements, instruction set and instruction formats of the processor are presented in suucient detail. The various trade-oos involved in the design are explained. Details of implementation of a scaled down version of the processor are presented.